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SY58021U
4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination Precision Edge(R)
General Description
The SY58021U is a 2.5V/3.3V precision, high-speed, fully differential 1:4 LVPECL fanout buffer. Optimized to provide four identical output copies with less than 15ps output skew and only 70 fsRMS phase jitter, the SY58021U can process clock signals as fast as 4GHz. The differential input includes Micrel's unique, 3-pin input termination architecture interfaces to differential LVPECL, CML, and LVDS signals (AC- or DC-coupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference voltage (VREFAC) is provided to bias the VT pin. The outputs are 100k LVPECL compatible, with extremely fast rise/fall times guaranteed to be less than 100ps. The SY58021U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require faster rise/fall times, or greater bandwidth, consider the SY58022U 1:4 fanout buffer with 400mV LVPECL output swing, or the SY58020U 1:4 CML fanout buffer. The (R) SY58021U is part of Micrel's high-speed, Precision Edge product line. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
Precision Edge(R)
Features
* Precision 1:4 LVPECL fanout buffer * Guaranteed AC performance-over-temperature/voltage: - >4GHz fMAX (clock) - <100ps tr/tf times - <300ps tPD - <15ps maximum skew * Low jitter performance: - 70fsRMS phase jitter (typical) * Accepts an input signal as low as 100mV * Unique input termination and VT pin accepts DCcoupled and AC-coupled differential inputs: LVPECL, LVDS, and CML * 100k LVPECL-compatible 800mV swing output * Power supply 2.5V 5% and 3.3V 10% * -40C to +85C temperature range * Available in 16-pin (3mm x 3mm) QFN package
Applications
* * * * All SONET and GigE clock distribution Fibre Channel clock and data distribution Backplane distribution High-end, low-skew, multiprocessor, synchronous clock distribution
Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
August 2010
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SY58021U
Ordering Information(1)
Part Number SY58021UMI SY58021UMITR SY58021UMG
(3) (2)
Package Type QFN-16 QFN-16 QFN-16
(2, 3)
Operating Range Industrial Industrial Industrial Industrial
Package Marking 021U 021U 021U with Pb-Free bar-line indicator 021U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
SY58021UMGTR
Notes: 1. 2. 3.
QFN-16
Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electrical only. Tape and Reel. Pb-Free package recommended for new designs.
Pin Configuration
16-Pin QFN
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SY58021U
Pin Description
Pin Number 1, 4 Pin Name IN, /IN Pin Function Differential Input: This input pair receives the signal to be buffered. Each pin of this pair internally terminates with 50 to the VT pin. Note that this input will default to an indeterminate state if left open. See "Input Interface Applications" section. Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to the termination network for maximum interface flexibility. See "Input Interface Applications" section. Reference Output Voltage: This output biases to VCC -1.2V. It is used when AC-coupling to differential inputs. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins as possible. Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. LVPECL Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 800mV Proper termination is 50 to VCC-2V at the receiving end. Unused output pairs may be left floating with no impact on jitter or skew. See "LVPECL Output Termination" section.
2
VT
3 8, 13 5, 16 14, 15, 11, 12, 9, 10, 6, 7
VREF-AC VCC GND, Exposed Pad /Q0, Q0, /Q1, Q1, /Q2, Q2, /Q3, Q3
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SY58021U
Absolute Maximum Ratings(1)
Power Supply Voltage (VCC)......................... -0.5V to +4.0V Input Voltage (VIN) ............................................ -0.5V to VCC LVPECL Output Current (IOUT) Continuous ............................................................ 50mA Surge .................................................................. 100mA Source or Sink Current on VT Pin VT Current ......................................................... 100mA Source or Sink Current on IN, /IN Input Current ....................................................... 50mA (4) Source or Sink Current on VREF-AC VREF Current ....................................................... 1.5mA Soldering (20s) ........................................................... 260C Storage Temperature (Ts) ......................... -65C to +150C
Operating Ratings(2)
Power Supply Voltage (VCC) .................. +2.375V to +3.60V Operating Temperature Range (TA) ............ -40C to +85C Package Thermal Resistance QFN (JA) Still-Air ....................................................... +60C/W 500 lpfm .................................................... +54C/W QFN (JB) (3) Junction-to-Board Resistance ................ +33C/W
Input DC Electrical Characteristics(5)
TA = -40C to +85C. Symbol VCC ICC VIH VIL VIN VDIFF_IN RIN VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. Due to the limited drive capability, use for input of the same package only. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. VIH (minimum) not lower than 1.2V.
Parameter Power Supply Voltage Power Supply Current Input HIGH Voltage Input LOW Voltage Input Voltage Swing Differential Input Voltage Swing IN-to-VT Resistance IN-to-VT Voltage Output Reference Voltage
Condition VCC = 2.5V VCC = 3.3V No load, VCC = maximum IN, /IN (Note 6) IN, /IN IN, /IN (see Figure 1a) IN, /IN (see Figure 1b)
Min. 2.375 3.0 VCC - 1.6 0 0.1 0.2 40 VCC - 1.30
Typ. 2.5 3.3 125
Max. 2.625 3.60 160 VCC VIH - 0.1 1.7
Units V mA V V V V V V
50 VCC - 1.2
60 1.28 VCC - 1.1
2. 3. 4. 5. 6.
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SY58021U
LVPECL Output DC Electrical Characteristics(5)
VCC = 3.3V 10% or 2.5 5%; RL = 50 to VCC - 2V; TA = -40C to +85C, unless otherwise stated. Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Differential Swing Differential Output Voltage Swing (see Figure 1a) (see Figure 1b) Condition Min. VCC - 1.145 VCC - 1.945 550 1100 780 1560 Typ. Max. VCC - 0.895 VCC - 1.695 1050 2100 Units V V mV mV
AC Electrical Characteristics
VCC = 2.5V 5% or 3.3 10%; RL = 50 to VCC - 2V; TA = -40C to +85C, unless otherwise stated. Symbol fMAX tPD tCHAN tSKEW tJITTER tr , tf
Notes: 7. 8. Skew is measured between outputs of the same bank under identical transitions. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
Parameter Maximum Operating Frequency Propagation Delay Channel-to-Channel Skew Part-to-Part Skew RMS Phase Jitter Output Rise/Fall Time (20% to 80%)
Condition VOUT 400mV Clock NRZ Data
Min. 4
Typ. 5
Max.
Units GHz Gbps
150 Note 7 Note 8 Output: 622MHz Integration Range: 12kHz - 20MHz At full swing 35
220 4
300 15 50
ps ps ps fs
70 75 110
ps
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SY58021U
Phase Noise Graph
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SY58021U
Timing Diagram
Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
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SY58021U
Typical Characteristics
VCC = 2.5V, GND = 0, VIN = 100mV, TA = 25C, unless otherwise stated.
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SY58021U
Functional Characteristics
VCC = 2.5V, GND = 0, VIN = 100mV, TA = 25C, unless otherwise stated.
Input Stage
Figure 2. Simplified Differential Input Buffer
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SY58021U
Input Interface Applications
Figure 3a. LVPECL Input Interface
Figure 3b. AC-Coupled LVPECL Input Interface
Figure 3c. LVDS Input Interface
Figure 3d. DC-Coupled CML Input Interface
Figure 3e. AC-Coupled CML Input Interface
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SY58021U
LVPECL Output
LVPECL outputs have very-low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques in terminating the LVPECL output (Figures 4 through 6).
Figure 4. Parallel Termination-Thevenin Equivalent
Figure 5. Parallel Termination (3-Resistor)
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SY58021U
Figure 6. Terminating Unused I/O
Related Micrel Products and Support Documentation
Part Number SY58020U SY58021U SY58022U M-0317 Function 6GHz, 1:4 CML Fanout Buffer/Translator with Internal I/O Terminations 4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination 5.5GHz, 1:4 Fanout Buffer/Translator with 400mV LVPECL Outputs and Internal Terminations HBW Solutions Data Sheet Link www.micrel.com/product-info/products/sy58020u.shtml www.micrel.com/product-info/products/sy58021u.shmtl www.micrel.com/product-info/products/sy58022u.shtml www.micrel.com/product-info/as/solutions.shtml
August 2010
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SY58021U
Package Information
16-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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